Conventional fabrication of integrated circuits generally requires the formation of multiple integrated circuit patterns, or fields, on one or more layers over a substrate wafer. These fields generally include numerous regions of micro-structures or nano-structures that are formed through photolithography, wet or dry etching processes, implantation or deposition processes, and the like. The relative positioning and alignment, or “overlay,” between such fields is an important component of ensuring the functionality of the resultant integrated circuit, and as such minimizing overlay errors is a significant concern in the manufacturing of circuit structures such as integrated circuits. Typically, the overlay error tolerance level between any two fields is less than 40% of the minimum “critical dimension,” or smallest feature size, of the fields, although some fields may demand even smaller overlay error tolerances.
Overlay metrology is one way to monitor overlay alignment and minimize overlay errors. This process generally forms overlay metrology target patterns, or simply “metrology patterns,” in the same layer as the functional circuit structure fields that the metrology patterns correspond to. These metrology patterns are generally formed in an inactive region of the wafer or device being processed, usually at the edge, and are formed by the same tool or process that forms the functional structures of the circuit structure field. The metrology patterns may then be scanned and/or imaged by an overlay metrology tool, and the metrology patterns of any two fields or layers measured and compared to determine their relative positions, with deviations in the overlay of the target patterns generally corresponding to deviations in the overlay between the circuit structure fields. Many different types of overlay metrology patterns have been developed to address issues with older overlay metrology patterns, including improving the accuracy of overlay metrology measurements, reducing processing errors that may affect overlay metrology, reducing the amount of space on a wafer necessary to obtain measurements and comparisons between each pairing of circuit structure fields, and so on. Existing overlay metrology target patterns generally may address some of these issues but at the cost of failing to address or exacerbating other issues. There is thus a continuing need to develop new overlay metrology patterns that can effectively address these issues, and thereby facilitate circuit structure fabrication.